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NSF/Intel Partnership on Foundational Microarchitecture Research
The confluence of transistor scaling, increases in the number of architecture designs per process generation, the slowing of clock frequency growth, and recent success in research exploiting thread-level parallelism (TLP) and data-level parallelism (DLP) all point to an increasing opportunity for innovative
microarchitecture techniques and methodologies in delivering performance growth in the future.
The NSF/Intel Partnership on Foundational Microarchitecture Research will support transformative microarchitecture research targeting improvements in instructions per cycle (IPC).
This solicitation seeks microarchitecture technique innovations beyond simplistic, incremental scaling of existing microarchitectural structures.
Specifically, FoMR seeks to advance research that has the following characteristics:
(1) high IPC techniques ranging from microarchitecture to code generation; (2) “microarchitecture turbo” techniques that marshal chip resources and system memory bandwidth to accelerate sequential or single-threaded programs; and (3) techniques to support efficient compiler code generation.
Advances in these areas promise to provide significant performance improvements that continue the trends characterized by Moore’s Law.
microarchitecture techniques and methodologies in delivering performance growth in the future.
The NSF/Intel Partnership on Foundational Microarchitecture Research will support transformative microarchitecture research targeting improvements in instructions per cycle (IPC).
This solicitation seeks microarchitecture technique innovations beyond simplistic, incremental scaling of existing microarchitectural structures.
Specifically, FoMR seeks to advance research that has the following characteristics:
(1) high IPC techniques ranging from microarchitecture to code generation; (2) “microarchitecture turbo” techniques that marshal chip resources and system memory bandwidth to accelerate sequential or single-threaded programs; and (3) techniques to support efficient compiler code generation.
Advances in these areas promise to provide significant performance improvements that continue the trends characterized by Moore’s Law.
Who's Eligible
Relevant Nonprofit Program Categories
Obtain Full Opportunity Text:
NSF Publication 19-598
Additional Information of Eligibility:
*Who May Submit Proposals: Proposals may only be submitted by the following: -Institutions of Higher Education (IHEs) - Two- and four-year IHEs (including community colleges) accredited in, and having a campus located in the US, acting on behalf of their faculty members.Special Instructions for International Branch Campuses of US IHEs: If the proposal includes funding to be provided to an international branch campus of a US institution of higher education (including through use of subawards and consultant arrangements), the proposer must explain the benefit(s) to the project of performance at the international branch campus, and justify why the project activities cannot be performed at the US campus.
Full Opportunity Web Address:
http://www.nsf.gov/publications/pub_summ.jsp?ods_key=nsf19598
Contact:
Agency Email Description:
If you have any problems linking to this funding announcement, please contact
Agency Email:
Date Posted:
2019-08-20
Application Due Date:
Archive Date:
2019-12-20
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